The present invention relates, in general, to the field of reconfigurable computing systems. More particularly, the present invention relates to a system and method for retaining dynamic random access memory (DRAM) data when reprogramming reconfigurable devices with DRAM memory controllers incorporating a data maintenance block collocated with a memory module or subsystem. In a further alternative embodiment of the present invention, a memory subsystem implemented in persistent memory is provided which utilizes a communication port coupled to a reconfigurable memory controller that advises the controller as to the current state of the memory as required by the controller.
The majority of today's programmable logic designs include a DRAM based memory solution at the heart of their memory subsystem. Today's DRAM devices are significantly faster than previous generation's, albeit at the cost of requiring increasingly complex and resource intensive memory controllers. One example is in double data rate 3 and 4 (DDR3 and DDR4) controllers which require read and write calibration logic. This added logic was not necessary when using previous versions of DRAM (e.g. DDR and DDR2. As a result, companies are forced to absorb substantial design costs and increased project completion times when designing proprietary DRAM controllers utilizing modern DRAM technology.
In order to mitigate design engineering costs and verification time, it is very common for field programmable gate array (FPGA) designers to implement vendor provided memory controller intellectual property (IP) when including DRAM based memory solutions in their designs. See, for example, Allan, Graham; “DDR IP Integration: How to Avoid Landmines in this Quickly Changing Landscape”; Chip Design, June/July 2007; pp 2022 and Wilson, Ron; “DRAM Controllers for System Designers”; Altera Corporation Articles, 2012.
FPGA designers tend to choose device manufacturer IP designs because they are proven, tested and have the incredible benefit of significantly reduced design costs and project completion times. Many times there is the added benefit of exploiting specialized circuitry within the programmable device to increase controller performance, which is not always readily apparent when designing a controller from scratch.
The downside to using factory supplied IP memory controllers is that there is little flexibility when trying to modify operating characteristics. A significant problem arises in reconfigurable computing when the FPGA is reprogrammed during a live application and the memory controller tri-states all inputs and outputs (I/O) between the FPGA device and the DRAM. The result is corrupted data in the memory subsystem. Therefore, dynamically reconfigurable processors are excluded as viable computing options, especially in regard to database applications or context switch processing. The reason for this is that the time it takes to copy the entire contents of DRAM data and preserve it in another part of the system, reconfigure the processor, then finally retrieve the data and restore it in DRAM is just too excessive.
Current state of the art reconfigurable computing systems will generally commence operations from a reset condition after the system is configured and initialize non-persistent (or volatile) memory subsystem. However, much development of enhancing persistent memory subsystems is currently underway. See for example, Lee, B. C. et al.; “Architecting Phase Change Memory as a Scalable DRAM Alternative”; ISCA June 2009. Persistent memories have the benefit of maintaining previously processed data when reconfiguring or hot-swapping memory controllers.
After reconfiguration, it would be beneficial for the processor section of the system to know the current status of the memory subsystem before it begins initializing the memory, especially in a context switch operation where the processor might require using the same data set between reconfigurations.